Carrier, semiconductor device, and method of their mounting

ABSTRACT

A carrier, semiconductor device, and their mounting method which improve reliability such as heat cycle resistance of the semiconductor device mounted on a circuit board. A semiconductor device 1 comprises a carrier for semiconductor 3, and a cavity area is formed at an area of an external electrode 8 of the carrier for semiconductor 3. The external electrode 8 is disposed at the bottom of the concave portion. A solder paste 13 is supplied to the concave portion, the semiconductor device 1 is flipped, and the semiconductor device 1 is mounted on the circuit board 12. The semiconductor 1 mounted on the circuit board 12 is heated to the temperature above the melting point of the solder paste 13.

FIELD OF THE INVENTION

The present invention relates to the field of semiconductor devices formounting semiconductor elements on circuit boards.

BACKGROUND OF THE INVENTION

A semiconductor device of the prior art is explained with reference todrawings.

In FIG. 8. a semiconductor device 1 consists of a semiconductor element2 disposed on a carrier 3 made of insulating material. A plurality ofelectrodes 6 soldered or bonded with a gold bump 5 to electrodes 4 ofthe semiconductor element 2 are disposed on the top face of the carrier3, and external electrode terminals 8 are aligned in a matrix on thebottom face of the carrier 3. The electrodes 6 are electrically coupledto external electrode terminals 8. The space between the semiconductorelement 2 and carrier 3. and around the semiconductor element 2 arefilled and covered with epoxy resin sealant 7. Solder bumps 9 may insome cases be formed on the surface of the external electrode terminals8. In FIG. 8, the semiconductor device is mounted on a circuit board 12.Electrodes 11 are disposed in the matrix on the circuit board 12 in anarea where the semiconductor device 1 will be mounted, corresponding tothe external electrode terminals 8. Solder paste 13 is printed on thematrix electrodes 11. As shown in FIG. 9, the semiconductor device 1 isplaced on the circuit board 12 so as to allow the external electrodeterminals 8 of the semiconductor device 1 to make contact with theelectrodes 11 of the circuit board 12. The external electrode terminals8 and electrodes 11 are bonded with solder 10 by heating and melting thesolder paste 13.

The design of the semiconductor device 1 as configured above makes itdifficult to adjust the height H between the carrier 3 and circuit board12, as shown in FIG. 9, when mounting the semiconductor device 1 ontothe circuit board 12. If the height H is short, thermal stress generatedby the difference in thermal expansion coefficient of the carrier 3 andcircuit board 12 is concentrated on the soldered portion, causing cracksin soldered portions or peeling in some cases.

DISCLOSURE OF THE INVENTION

The present invention offers a semiconductor device which can be mountedon a printed circuit board with high reliability, and a mounting methodfor such semiconductor devices.

In the semiconductor device of the present invention, output electrodesformed on the surface of semiconductor elements which forms anintegrated circuit is connected to a conductive circuit formed on acarrier for semiconductor for enabling electrical coupling with anexternal material using external electrodes formed on the carrier forsemiconductor. The external electrodes are disposed on a bottom surfaceof cavity areas provided in the carrier for semiconductor.

The carrier for semiconductor has a multi-layer structure from the upperpart to the lower part protruding to the bottom face, In the thicknessdirection of the semiconductor device, for forming the concave portionwith the upper part of the flat board. Materials used for forming themulti-layer structure has different thermal expansion coefficients whichbridge the thermal expansion coefficient of the carrier forsemiconductor of the semiconductor device to the circuit board on whichthe semiconductor device is mounted.

A method for mounting the semiconductor device comprises the dispensingof solder paste to the concave portion of the external electrode of thesemiconductor device, flipping of the semiconductor device, mounting ofthe semiconductor device onto the circuit board, and soldering byheating the circuit board. Another method comprises application ofadhesive flux to the concave portion of the external electrode of thesemiconductor device, supplying of solder balls on top of the adhesiveflux applied, flipping of the semiconductor device, mounting of thesemiconductor device onto the circuit board, and soldering by heatingthe circuit board. Still another method comprises application ofadhesive to an area where electrical coupling is not required but thesemiconductor device contacts the circuit board when the electrodeprovided on the concave portion of the semiconductor device and theelectrode of the circuit board are electrically coupled, mounting of thesemiconductor device onto the circuit board, and soldering by heatingthe circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a perspective of a semiconductor device with a carrier inaccordance with a first exemplary embodiment of the present invention.

FIG. 1B is a section view seen at A--A of FIG. 1A.

FIG. 1C is a bottom view of FIG. 1A.

FIG. 2A is a perspective of a semiconductor device with a carrier inaccordance with a second exemplary embodiment of the present invention.

FIG. 2B is a section view seen at A--A of FIG. 2A.

FIG. 2C is a bottom view of FIG. 2A

FIG. 3A is a perspective of a semiconductor device with a carrier inaccordance with a third exemplary embodiment of the present invention.

FIG. 3B is a section view seen at A--A of FIG. 3A.

FIG. 3C is a bottom view of FIG. 3A.

FIGS. 4A to 4D are a process chart of a mounting method for asemiconductor device in accordance with the first exemplary embodimentof the present invention.

FIGS. 5A to 5D are a process chart of a mounting method for asemiconductor device in accordance with the second exemplary embodimentof the present invention.

FIGS. 6A to 6E are a process chart of a mounting method is for asemiconductor device in accordance with the third exemplary embodimentof the present invention.

FIG. 7 is a table of thermal expansion coefficients of a material usedin a semiconductor device of the exemplary embodiments of the presentinvention.

FIG. 8 is a side view of a configuration of a semiconductor device ofthe prior art.

FIG. 9 is a side view of a configuration of a conventional semiconductordevice mounted onto a circuit board.

DESCRIPTION OF THE PREFERRED EMBODIMENTS First Exemplary Embodiment

FIGS. 1A to 1C show the configuration of a semiconductor device 1employing a carrier in a first exemplary embodiment of the presentinvention. A specified circuit is formed in a semiconductor element 2itself, and an electrode 4 is formed on a part of the semiconductorelement 2. A carrier 3 is made of an insulating substrate 17, and thesemiconductor element 2 is disposed on the carrier 3. A second electrode6 is disposed on the top surface (other face) of the carrier 3 which iselectrically coupled to the electrode 4 on the semiconductor element 2.An external electrode terminal 8, which is the first electrode, isdisposed in the matrix on the bottom surface (one face) of the carrier 3as shown in FIG. 1C. The external electrode terminal 8 is electricallycoupled to the second electrode 6. A filling area 18 is formed on thebottom surface of the carrier (or insulating material 17) ina concavefashion. The filling area 18 will be filled with a bonding material suchas solder in a later process. The external electrode terminal 8 isdisposed at the bottom of the filling area 18. A sealant 7 fills andcovers the space between the semiconductor element 2 and carrier 3, andaround the semiconductor element 2. Here, the depth of the filling areais determined based on the desirable height for bonding thesemiconductor device 1 or carrier 3 to a board with a specified circuit(hereafter referred to as the "circuit board") in a later process. Thereis a range of methods for forming the concave filling area 18. Forexample, a cavity area may be formed by exposure and development using aphotosensitive epoxy resin film. The depth of the filling area 18 ispreferably 0.2 mm to 1.0 mm if the alignment pitch of the externalelectrode terminal (i.e., the distance between the center of adjacentexternal electrode terminals 8) is 1 mm and its diameter (i.e., thediameter of the external electrode terminal 8) is 0.5 mm. The carrier 3is generally made of alumina and ceramic such as glass ceramic, but itmay also be made of resin material such as epoxy resin.

When a semiconductor device as configured above is electrically bondedto a circuit board by means such as soldering, the height H of thebonded portion can be adjusted as required by changing the depth of thefilling area 18. This allows the securing of a greater height H betweenthe circuit board and the external electrode terminal 8, compared to thecase of mounting a semiconductor device without the filling area ontothe circuit board, thereby reducing the stress applied to the bondedface of the external electrode terminal 8 and improving reliability andthermal heat cycle resistance.

The thermal heat cycle resistance here is checked by applying thermalstress to a test piece by repeatedly alternating the ambient temperaturesurrounding the test piece between high and low. No cracks have beennoticed in the soldered portion of the semiconductor device of thepresent invention after repeating a cycle of +80° C. for 30 minutes and-40° C. for 30 minutes for 1,000 times.

In addition, when the semiconductor device 1 without the filling area 18is mounted on the circuit board, the solder used for electrical couplingforms a convex drum shape as shown in FIG. 9. With the carrier 3 or thesemiconductor device 1 of the present invention, soldering takes placeafter solder paste or solder balls are provided to the filling area 18,thus enabling the solder to form an hourglass shape with the concavecentral section in the height direction of bonding. This transfers thestress conventionally focused on the bonded surface to the center partof the bonded portion, allowing improvement of bonding strength andprevention of destruction of the bonded surface.

Second Exemplary Embodiment

FIGS. 2A to 2C show a configuration of the semiconductor device 1 with acarrier in a second exemplary embodiment of the present invention. Partsconfigured identically to the first exemplary embodiment are given thesame numeral codes, and thus their explanation is omitted.

The carrier 3 comprises a control material 52 from the bottom face (aninsulating material 51 which is a substrate) of the semiconductor device1 where the filling area 18 (control material 52) is provided (one face)to the bottom surface in the thickness direction of the semiconductordevice 1, and a flat insulating material 51 without any concave portion.The external electrode terminal 8, the first electrode, is disposed onthe insulating material 51 at the side where the control material 52 isprovided. The second electrode 6 is disposed on the insulating material51 at the side where the control material 52 is not provided (otherface). The external electrode terminal 8 and electrode 6 areelectrically coupled. The control material 52 is disposed around theexternal electrode terminal 8, and comprises the external electrodeterminal 8 as its bottom, thus forming the filling area 18. The fillingarea 18 controls the bonding material when applying a bonding materialsuch as solder to the external electrode terminal 8.

The insulating material 51 and the control material 52 in this exemplaryembodiment are made of different materials. A material of thermalexpansion coefficient closer to that of the semiconductor element 2 thanthat of the resin is used for the insulating material 51 of the carrier3. For example, if the semiconductor element 2 employs a siliconesubstrate, the insulating material 51 may be made of ceramic such asglass ceramic or a mixture of alumina and glass. Alumina may be used forthe insulating material 51 and control material 52.

A material of thermal expansion coefficient midway between that of thecircuit board on which the semiconductor device 1 is mounted and that ofthe insulating material 51 is used for the control material 52 of thecarrier 3. This will ease the thermal stress between the semiconductorelement 2, insulating material 51, control material 52, and the circuitboard, and improve the reliability of the structure after applying abonding material such as solder to the external electrode terminal 8 ina later process. If, for example, the insulating material 51 is made ofglass ceramic, a heat-resistant engineering plastic such aspolyphenylene sulfide may be used for the control material 52.

The above configuration further reduces the stress applied to the bondedportion in addition to the benefits of the first exemplary embodiment.

Third Exemplary Embodiment

FIGS. 3A to 3C show a configuration of a semiconductor device 1 with acarrier in a third exemplary embodiment of the present invention. Partsconfigured the same as the first exemplary embodiment are given the samenumeral codes, and thus their explanation is omitted.

The carrier 3 comprises the control material 52 and insulating material51 in the same way as in the second exemplary embodiment. The controlmaterial 52 consists of several layers 53 to 55 in the thicknessdirection, made of several materials. The layers in the control material52 are configured so that their thermal expansion coefficients form astepwise, positively correlated gradient between the thermal expansioncoefficient of the insulating material 51 and that of the circuit boardon which the semiconductor device 1 will be mounted in a later process

Materials comprising the control material 52 are made of polyphenylenesulfide mixed with filler (e.g., glass fiber), and their thermalexpansion coefficient is adjusted by changing the type and volume of thefiller. In this exemplary embodiment, the filler consists of about 60%of the entire material in the first layer 53 of the control material 52,about 50% in the second layer 54, and about 40% in the third layer 55.The thermal expansion coefficient increases as the percentage of thefiller to the entire volume is reduced. The layers 53, 54, and 55 arebonded with adhesive.

The above configuration enables further reduction of the stress appliedto the bonded portion in addition to the benefits achieved by the firstexemplary embodiment. The thermal expansion coefficients of thematerials used in this exemplary embodiment are shown in FIG. 7.

The thermal expansion coefficient in this exemplary embodiment variesstepwise in the thickness direction from the insulating material 51.However, the same effect can be achieved by linearly varying the thermalexpansion coefficient.

Fourth Exemplary Embodiment

A method for mounting the semiconductor device 1 of the presentinvention onto the circuit board is explained with reference to FIGS. 4Ato 4D.

First, the semiconductor device 1 is flipped to position the opening 19in the filling area 18 of the carrier 3 upwards for injecting solderpaste 13 (i.e., a pasty mixture of solder powder and flux) into thefilling area 18 as shown in FIG. 4A. The solder paste 13 is supplied byusing a mask with openings corresponding to the opening 19 of thefilling area 18. The mask is placed on the semiconductor device 1 withits openings positioned onto the opening 19, and solder paste 13 issupplied by printing it using a squeegee (i.e., a rubber spatula usedfor solder printing). The semiconductor device 1 filled with the solderpaste 13 is then flipped again to position the filling area 18 of thecarrier 3 filled with the solder paste 13 downwards.

As shown in FIG. 4B, the solder paste 13 is also printed on a circuitboard 12 on which the semiconductor device 1 will be mounted, using amask.

Next, the semiconductor device 1 is mounted on the circuit board 12after being positioned as shown in FIG. 4C. During the reflow process(i.e., a soldering method carried out by melting the solder using hotair or heat), the circuit board 12 is heated above the melting point ofthe solder paste for soldering the external electrode terminal 8 andelectrode 11 of the circuit board 12 by melting the solder paste. Ingeneral, for eutectic solder, the temperature is increased to 220° C.The volume of solder paste drops approximately by half due toevaporation of the flux in the solder paste during melting. When thesemiconductor device 1 and circuit board 12 are cooled to roomtemperature after soldering, the soldered portion shows an hourglassshape with a concave central section in the bonding height direction asshown in FIG. 4D. Metals also lose about 10% of their volume duringsolidification.

The solder paste 13 can be supplied into the filling area 18 withoutusing a mask as explained in this exemplary embodiment. For example, thesolder paste 13 can be supplied by applying the solder paste 13 directlyto the carrier 3 and using the squeegee to remove the excess.

This exemplary embodiment also employs a mask for printing the solderpaste 13 on the circuit board 12 because electronic components otherthan the semiconductor device 1 of the present invention, such asresistors and capacitors, are generally mounted together with thesemiconductor device 1. However, since the solder paste 13 is alreadysupplied to the filling area 18 of the carrier 3, printing of the solderpaste 13 onto the circuit board 12 may not always be necessary formounting the semiconductor device 1. Whether to print the solder paste13 on the circuit board 12 for the semiconductor device 1 depends onwhether an opening is provided on the mask or not, and therefore themounting process itself is always the same.

The mounting method of this exemplary embodiment can be employed formounting the semiconductor device with carrier in any of the first,second, and third exemplary embodiments.

With the use of this mounting method, the effect described in the firstto third exemplary embodiments can be achieved.

Fifth Exemplary Embodiment

Another method for mounting a semiconductor device of the presentinvention is explained with reference to FIG. 5.

First, the semiconductor device is flipped to position the opening 19 onthe filling area 18 disposed on the carrier 3 face upwards, adhesiveflux 15 is applied to the external electrode terminal 8, and solderballs 16 are supplied over the adhesive flux 15.

In this exemplary embodiment isopropyl alcohol is used as adhesive fluxand solvent, abietic acid as rosin, and ethyl amine hydrochloride as anactivator. Other suitable substances, however, may also be utilized.

The adhesive flux 15 is dispensed, and the solder balls 16 are suppliedby a mounter placing electronic components. However, other suitablemethods may also be utilized. The dispensing means can be, for example,the supply of adhesive flux 15 to a syringe-like container, whereinadhesive flux 15 from a needle tip is extruded to one side by applyingpressure to the adhesive flux 15 from the other side.

The semiconductor device 1 supplied with the solder balls 16 is thenflipped again to position the filling area of the carrier 3 suppliedwith the solder balls 16 downwards.

Meanwhile, the solder paste 13 is printed using a mask on the circuitboard 12 on which the semiconductor device 1 will be mounted.

Next, the semiconductor device 1 is positioned on the circuit board 12,and mounted. In the reflow process, the solder paste 13 is then meltedto solder the external electrode terminal 8 and the electrode 11 of thecircuit board 12 by heating it to a temperature above the melting pointof the solder paste 13. In general, for eutectic solder, the temperatureis increased to 220° C. Since solder paste loses volume when fused, thesoldered portion forms an hourglass shape with a concave central sectionin the height direction when it is cooled down to room temperature aftersoldering as shown in FIG. 5D.

This exemplary embodiment is applicable for mounting the carrier andsemiconductor device described in the first, second, and third exemplaryembodiments.

In this exemplary embodiment, the solder paste 13 is printed on thecircuit board 12 using the mask, but the process for printing the solderpaste 13 on the circuit board 12 is not always necessary for mountingthe semiconductor device 1 as in the fourth exemplary embodiment.

With the use of this mounting method, the advantage described in thefirst to third exemplary embodiments can be achieved.

Sixth Exemplary Embodiment

Still another method for mounting the semiconductor device 1 of thepresent invention is described with reference to FIG. 6.

First, the semiconductor device 1 is flipped to position the opening 19on the filling area 18 of the carrier 3 upwards, and the filling area 18is filled with the solder paste 13 as shown in FIG. 6A.

Adhesive 14 is applied to a contacting area 20 on the circuit board 12where electrical coupling is not required when the semiconductor 1contacts the circuit board 12. The adhesive 14 may be applied to thecarrier 3 side.

The solder paste 13 is supplied by using a mask with openingscorresponding to the opening 19 of the filling area 18. The mask isplaced on the semiconductor device 1 with its openings positioned ontothe opening 19, and solder paste 13 is supplied by printing it using asqueegee. The semiconductor device 1 filled with the solder paste 13 isthen flipped again to position the filling area 18 of the carrier 3filled with the solder paste 13 downwards. The solder paste 13 isprinted on the circuit board 12 on which the semiconductor device 1 willbe mounted using a mask as shown in FIG. 6B.

Next, the semiconductor device 1 is positioned on the circuit board 12,and mounted. In the reflow process (i.e. a soldering method carried outby melting the solder using hot air or heat), the solder paste 13 ismelted to solder the external electrode terminal 8 and the electrode 11of the circuit board 12 by heating it to a temperature above the meltingpoint of the solder paste 13. In general, for eutectic solder, thetemperature is increased to 220° C. Since solder paste loses volume whenfused, the soldered portion forms an hourglass shape with a concavecentral section in the height direction when it is cooled down to roomtemperature after soldering as shown in FIG. 6E

Accordingly, the semiconductor device 1 contacts the circuit board 12,and the area not requiring electrical coupling is bonded to the circuitboard 12 with adhesive. The adhered area absorbs the stress at heatingfor soldering, and thus reduces the stress applied to the electricallybonded portion.

The solder paste 13 can be supplied into the filling area 18 withoutusing a mask as explained in this exemplary embodiment. For example, thesolder paste 13 can be supplied by applying the solder paste 13 directlyto the carrier 3, and using the squeegee to remove the excess.

This exemplary embodiment also employs a mask for printing the solderpaste 13 on the circuit board 12 Howeverthe process of printing thesolder paste 13 on the circuit board 12 may not always be necessary formounting the semiconductor device 1, same as in the fourth exemplaryembodiment.

With the use of this mounting method, the advantage described in thefirst to third exemplary embodiments can be achieved.

INDUSTRIAL APPLICABILITY

The carrier or semiconductor device of the present invention allows thecontrol of the height H of a bonded portion by adjusting the depth ofthe cavity area when electrically coupling, including soldering, to acircuit board. The height H of the bonded portion can be made greater ascompared to mounting a semiconductor device without the cavity area,thereby reducing the stress applied to the bonded surface and improvingreliability and thermal heat cycle resistance.

In addition, the present invention enables the formation of an hourglassshape with a concave central section in the thickness direction at thesoldered portion by filling the filling area with solder paste or solderballs before soldering. In the prior art, a semiconductor device withoutthe filling area forms a convex drum shape at the soldered portion. Thesoldered portion in the present invention forms an hourglass shapebecause the volume of solder shrinks when the solder paste melts. Thehourglass shape transfers the stress concentrated on the bonded surfaceto its central section, improving the bonding strength and preventingdestruction of the bonded surface.

In the case of electrically coupling the cavity area provided on acarrier for the semiconductor and the electrode on the circuit board, anadhered portion absorbs the stress, reducing the stress applied to theelectrically coupled portion, by attaching an area where thesemiconductor device and the circuit board contact but electricalcoupling is not required with adhesive, and heating and soldering thesemiconductor device onto the circuit board.

The present invention also enables the reduction of the stress appliedto the adhered portion and thus reduces the stress applied to theelectrically coupled portion by forming a part from the electrode at thebottom of the concave portion provided on the carrier for semiconductorof the semiconductor device to the surface of the side where there is nosemiconductor element using layers comprising materials with differentthermal expansion coefficients which bridge, in a stepwise fashion, thethermal expansion coefficient of the carrier for semiconductor of thesemiconductor device to the circuit board on which the semiconductordevice is mounted.

What is claimed is:
 1. A carrier comprising:a substrate provided with acavity area on one face; a first electrode provided at the bottom ofsaid cavity area of said substrate such that said first electrodeoccupies only said bottom of said cavity and is completely disposedwithin said cavity, said cavity operative for receiving a bondingmaterial which is bonded onto said first electrode; and a secondelectrode provided on the other face of said substrate such that saidfirst electrode and said second electrode are vertically aligned withone another; said first electrode and said second electrode beingelectrically coupled through an opening disposed on said bottom.
 2. Acarrier comprising:a first electrode provided at one face of asubstrate; a second electrode provided on the other face of saidsubstrate and electrically coupled to said first electrode provided onone face of said substrate through an opening provided at the bottomthereof, said first electrode and said second electrode being verticallyaligned with one another; a control material provided around said firstelectrode so as to form a filling area, said filling area having saidfirst electrode only at the bottom thereof, said filling area operativefor receiving bonding material which is bonded onto said firstelectrode, said first electrode being completely disposed within saidfilling area.
 3. A carrier according to claim 1, further comprisingbonding material disposed within said cavity.
 4. A carrier according toclaim 2, further comprising bonding material disposed within saidfilling area.
 5. A carrier as defined in claim 2, wherein said substrateand said filling area are made of materials having different thermalexpansion coefficients.
 6. A carrier as defined in claim 2, wherein athermal expansion coefficient of said control material at the side ofsaid substrate is close to the thermal expansion coefficient of saidsubstrate, and the thermal expansion coefficient of said controlmaterial is graded, in the thickness direction, toward close to thethermal expansion coefficient of a board on which to be mounted.
 7. Asemiconductor device having electrical coupling among a semiconductorelement having a specified circuit and an electrode therein, saidelectrode of the semiconductor element, and a first electrode of acarrier as defined in one of claims 1 to
 6. 8. A carrier comprising:asubstrate provided with a cavity area on one face; a first electrodeprovided at the bottom of said cavity area of said substrate such thatsaid first electrode is completely disposed within said cavity, whereina majority of said cavity is operative for receiving a bonding materialwhich is bonded onto said first electrode; and a second electrodeprovided on the other face of said substrate such that said firstelectrode and said second electrode are vertically aligned with oneanother; said first electrode and said second electrode beingelectrically coupled through an opening disposed on said bottom.
 9. Acarrier comprising:a first electrode provided at one face of asubstrate; a second electrode provided on the other face of saidsubstrate and electrically coupled to said first electrode provided onone face of said substrate through an opening provided at the bottomthereof, said first electrode and said second electrode being verticallyaligned with one another; a control material provided around said firstelectrode so as to form a filling area, said filling area having saidfirst electrode at the bottom thereof, a majority of said filling areabeing operative for receiving bonding material which is bonded onto saidfirst electrode, said first electrode being completely disposed withinsaid filling area.